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1/25 may 2002 m48t35ay M48T35AV 5.0 or 3.3v, 256 kbit (32 kb x 8) timekeeper ? sram features summary n integrated, ultra low power sram, real time clock, power-fail control circuit and battery n bytewide? ram-like clock access n bcd coded year, month, day, date, hours, minutes, and seconds n battery low flag (bok ) n frequency test output for real time clock n automatic power-fail chip deselect and write protection n write protect voltages (v pfd = power-fail deselect voltage): C m48t35ay: v cc = 4.5 to 5.5v 4.2v v pfd 4.5v C M48T35AV: v cc = 3.0 to 3.6v 2.7v v pfd 3.0v n self-contained battery and crystal in the caphat? dip package n soic package provides direct connection for a snaphat ? housing containing the battery and crystal n snaphat ? housing (battery and crystal) is replaceable n pin and function compatible with jedec standard 32kb x 8 srams figure 1. 28-pin, pcdip caphat? package figure 2. 28-pin soic package 28 1 pcdip28 (pc) battery/crystal caphat 28 1 snaphat (sh) battery/crystal soh28 (mh)
m48t35ay, M48T35AV 2/25 table of contents summarydescription...........................................................4 logicdiagram(figure3.).........................................................4 signalnames(table1.)..........................................................4 dip connections (figure 4.) .......................................................5 soic connections (figure 5.) ......................................................5 blockdiagram(figure6.).........................................................5 maximumrating.................................................................6 absolutemaximumratings(table2.) ...............................................6 dc and ac parameters. . ........................................................7 operating and ac measurement conditions (table 3.) ..................................7 acmeasurementloadcircuit(figure7.).............................................7 capacitance (table 4.) . . . ........................................................7 dccharacteristics(table5.) ......................................................8 operationmodes...............................................................9 operating modes (table 6.) ........................................................9 readmode...................................................................10 readmodeacwaveforms(figure8.).............................................10 readmodeaccharacteristics(table7.)...........................................10 writemode..................................................................11 write enable controlled, write mode ac waveform (figure 9.) . .......................11 chipenablecontrolled,writemodeacwaveforms(figure10.)........................11 writemodeaccharacteristics(table8.) ..........................................12 dataretentionmode............................................................13 checkingthebokflagstatus(figure11.) ..........................................13 powerdown/upmodeacwaveforms(figure12.) ....................................14 powerdown/upaccharacteristics(table9.)........................................14 powerdown/uptrippointsdccharacteristics(table10.)..............................14
3/25 m48t35ay, M48T35AV clockoperations.............................................................15 reading the clock . .............................................................15 registermap(table11.).........................................................15 settingtheclock...............................................................15 stopping and starting the oscillator ................................................15 calibratingtheclock............................................................16 centurybit....................................................................16 v cc noise and negative going transients . ..........................................17 supplyvoltageprotection(figure13.)..............................................17 crystalaccuracyacrosstemperature(figure14.) ....................................18 clockcalibration(figure15.) .....................................................18 partnumbering ...............................................................19 snaphatbatterytable(table13.)................................................19 package mechanical information . . . ..........................................20 revisionhistory...............................................................24
m48t35ay, M48T35AV 4/25 summary description the m48t35ay/v timekeeper ? ram is a 32kb x 8 non-volatile static ram and real time clock. the monolithic chip is available in two special packages to provide a highly integrated battery backed-up memory and real time clock solution. the m48t35ay/v is a non-volatile pin and func- tion equivalent to any jedec standard 32kb x 8 sram.italsoeasilyfitsintomanyrom,eprom, and eeprom sockets, providing the non-volatility of proms without any requirement for special write timing or limitations on the number of writes that can be performed. the 28-pin, 600mil dip caphat? houses the m48t35ay/v silicon with a quartz crystal and a long-life lithium button cell in a single package. the 28-pin, 330mil soic provides sockets with gold plated contacts at both ends for direct con- nection to a separate snaphat ? housing con- taining the battery and crystal. the unique design allows the snaphat battery package to be mounted on top of the soic package after the completion of the surface mount process. inser- tion of the snaphat housing after reflow pre- vents potential battery and crystal damage due to the high temperatures required for device surface- mounting. the snaphat housing is keyed to pre- vent reverse insertion. the soic and battery/crystal packages are shipped separately in plastic anti-static tubes or in tape & reel form. for the 28-lead soic, the battery/crystal package (e.g. snaphat) part number is m4t28-br12sh (see table 13, page 19). figure 3. logic diagram table 1. signal names ai02797b 15 a0-a14 w dq0-dq7 v cc m48t35ay M48T35AV g v ss 8 e a0-a14 address inputs dq0-dq7 data inputs / outputs e chip enable g output enable w write enable v cc supply voltage v ss ground
5/25 m48t35ay, M48T35AV figure 4. dip connections figure 5. soic connections figure 6. block diagram a1 a0 dq0 a7 a4 a3 a2 a6 a5 a13 a10 a8 a9 dq7 w a11 g e dq5 dq1 dq2 dq3 v ss dq4 dq6 a12 a14 v cc ai02798b 8 1 2 3 4 5 6 7 9 10 11 12 13 14 16 15 28 27 26 25 24 23 22 21 20 19 18 17 m48t35ay M48T35AV ai02799 8 2 3 4 5 6 7 9 10 11 12 13 14 22 21 20 19 18 17 16 15 28 27 26 25 24 23 1 a1 a0 dq0 a7 a4 a3 a2 a6 a5 a13 a10 a8 a9 dq7 w a11 g e dq5 dq1 dq2 dq3 v ss dq4 dq6 a12 a14 v cc m48t35ay M48T35AV ai01623 lithium cell oscillator and clock chain v pfd v cc v ss 32,768 hz crystal voltage sense and switching circuitry 8 x 8 biport sram array 32,760 x 8 sram array a0-a14 dq0-dq7 e w g power
m48t35ay, M48T35AV 6/25 maximum rating stressingthedeviceabovetheratinglistedinthe absolute maximum ratings table may cause permanent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicat- ed in the operating sections of this specification is not implied. exposure to absolute maximum rat- ing conditions for extended periods may affect de- vice reliability. refer also to the stmicroelectronics sure program and other rel- evant quality documents. table 2. absolute maximum ratings note: 1. for dip package: soldering temperature not to exceed 260c for 10 seconds (total thermal budget not to exceed 150c for longer than 30 seconds). 2. for so package: reflow at peak temperature of 215c to 225c for < 60 seconds (total thermal budget not to exceed 180c for between 90 to 120 seconds). caution: negative undershoots below C0.3v are not allowed on any pin while in the battery back-up mode. caution: do not wave solder soic to avoid damaging snaphat sockets. symbol parameter value unit t a ambient operating temperature grade 1 0 to 70 c grade 6 C40 to 85 c t stg storage temperature (v cc off, oscillator off) C40 to 85 c t sld (1,2) lead solder temperature for 10 seconds 260 c v io input or output voltages m48t35ay C0.3 to 7 v M48T35AV C0.3 to 4.6 v v cc supply voltage m48t35ay C0.3 to 7 v M48T35AV C0.3 to 4.6 v i o output current 20 ma p d power dissipation 1 w
7/25 m48t35ay, M48T35AV dc and ac parameters this section summarizes the operating and mea- surement conditions, as well as the dc and ac characteristics of the device. the parameters in the following dc and ac characteristic tables are derived from tests performed under the measure- ment conditions listed in the relevant tables. de- signers should check that the operating conditions in their projects match the measurement condi- tions when using the quoted parameters. table 3. operating and ac measurement conditions note: output hi-z is defined as the point where data is no longer driven. figure 7. ac measurement load circuit note: 50pf for M48T35AV. table 4. capacitance note: 1. effective capacitance measured with power supply at 5v; sampled only, not 100% tested. 2. at 25c, f = 1mhz. 3. outputs deselected. parameter m48t35ay M48T35AV unit supply voltage (v cc ) 4.5 to 5.5 3.0 to 3.6 v ambient operating temperature (t a ) grade 1 0 to 70 0 to 70 c grade 6 C40 to 85 C40 to 85 load capacitance (c l ) 100 50 pf input rise and fall times 5 5ns input pulse voltages 0 to 3 0 to 3 v input and output timing ref. voltages 1.5 1.5 v ai02586 c l = 100pf (or 5pf) c l includes jig capacitance 645 w device under test 1.75v symbol parameter (1,2) min max unit c in input capacitance 10 pf c out (3) output capacitance 10 pf
m48t35ay, M48T35AV 8/25 table 5. dc characteristics note: 1. valid for ambient operating temperature: t a = 0 to 70c or C40 to 85c; v cc = 4.5 to 5.5v or 3.0 to 3.6v (except where noted). 2. outputs deselected. 3. negative spikes of C1v allowed for up to 10ns once per cycle. symbol parameter test condition (1) m48t35ay M48T35AV unit C70 C100 min max min max i li input leakage current 0v v in v cc 1 1 a i lo (2) output leakage current 0v v out v cc 1 1 a i cc supply current outputs open 50 30 ma i cc1 supply current (standby) ttl e =v ih 32ma i cc2 supply current (standby) cmos e =v cc C 0.2v 32ma v il (3) input low voltage C0.3 0.8 C0.3 0.8 v v ih input high voltage 2.2 v cc + 0.3 2.2 v cc +0.3 v v ol output low voltage i ol = 2.1ma 0.4 0.4 v v oh output high voltage i oh = C1ma 2.4 2.4 v
9/25 m48t35ay, M48T35AV operation modes as figure 6, page 5 shows, the static memory ar- ray and the quartz controlled clock oscillator of the m48t35ay/v are integrated on one silicon chip. the two circuits are interconnected at the upper eight memory locations to provide user accessible bytewide? clock information in the bytes with addresses 7ff8h-7fffh. the clock locations contain the year, month, date, day, hour, minute, and second in 24 hour bcd for- mat. corrections for 28, 29 (leap year - valid until 2100), 30, and 31 day months are made automat- ically. byte 7ff8h is the clock control register. this byte controls user access to the clock information and also stores the clock calibration setting. the eight clock bytes are not the actual clock counters themselves; they are memory locations consisting of biport? read/write memory cells. the m48t35ay/v includes a clock control circuit which updates the clock bytes with current information once per second. the information can be accessed by the user in the same manner as any other location in the static memory array. the m48t35ay/v also has its own power-fail de- tect circuit. the control circuitry constantly moni- tors the single 3v supply for an out of tolerance condition. when v cc is out of tolerance, the circuit write protects the sram, providing a high degree of data security in the midst of unpredictable sys- tem operation brought on by low v cc .asv cc falls below the battery back-up switchover voltage (v so ), the control circuitry connects the battery which maintains data and clock operation until val- id power returns. table 6. operating modes note: x = v ih or v il ;v so = battery back-up switchover voltage. 1. see table 10, page 14 for details. mode v cc e g w dq0-dq7 power deselect 4.5 to 5.5v or 3.0 to 3.6v v ih x x high z standby write v il x v il d in active read v il v il v ih d out active read v il v ih v ih high z active deselect v so to v pfd (min) (1) x x x high z cmos standby deselect v so (1) x x x high z battery back-up mode
m48t35ay, M48T35AV 10/25 read mode the m48t35ay/v is in the read mode whenever w (write enable) is high and e (chip enable) is low. the unique address specified by the 15 ad- dress inputs defines which one of the 32,768 bytes of data is to be accessed. valid data will be avail- able at the data i/o pins within address access time (t avqv ) after the last address input signal is stable, providing that the e and g access times are also satisfied. if the e and g access times are not met, valid data will be available after the latter of the chip enable access time (t elqv ) or output enable access time (t glqv ). the state of the eight three-state data i/o signals is controlled by e and g . if the outputs are activat- ed before t avqv , the data lines will be driven to an indeterminate state until t avqv . if the address in- puts are changed while e and g remain active, output data will remain valid for output data hold time (t axqx ) but will go indeterminate until the next address access. figure 8. read mode ac waveforms note: write enable (w )=high. table 7. read mode ac characteristics note: 1. valid for ambient operating temperature: t a = 0 to 70c or C40 to 85c; v cc = 4.5 to 5.5v or 3.0 to 3.6v (except where noted). 2. c l = 5pf. symbol parameter (1) m48t35ay M48T35AV unit C70 C100 minmaxminmax t avav read cycle time 70 100 ns t av qv address valid to output valid 70 100 ns t elqv chip enable low to output valid 70 100 ns t glqv output enable low to output valid 35 50 ns t elqx (2) chip enable low to output transition 5 10 ns t glqx (2) output enable low to output transition 5 5 ns t ehqz (2) chip enable high to output hi-z 25 50 ns t ghqz (2) output enable high to output hi-z 25 40 ns t axqx address transition to output transition 10 10 ns ai00925 tavav tavqv taxqx telqv telqx tehqz tglqv tglqx tghqz valid a0-a14 e g dq0-dq7 valid
11/25 m48t35ay, M48T35AV write mode the m48t35ay/v is in the write mode whenev- er w and e are low. the start of a write is refer- enced from the latter occurring falling edge of w or e . a write is terminated by the earlier rising edge of w or e . the addresses must be held valid throughout the cycle. e or w must return high for aminimumoft ehax from chip enable or t whax from write enable prior to the initiation of anoth- er read or write cycle. data-in must be valid t d- vwh prior to the end of write and remain valid for t whdx afterward. g should be kept high during write cycles to avoid bus contention; however, if the output bus has been activated by a low on e and g ,alowonw will disable the outputs t wlqz after w falls. figure 9. write enable controlled, write mode ac waveform figure 10. chip enable controlled, write mode ac waveforms ai00926 tavav twhax tdvwh data input a0-a14 e w dq0-dq7 valid tavwh tavel twlwh tavwl twlqz twhdx twhqx ai00927 tavav tehax tdveh a0-a14 e w dq0-dq7 valid taveh tavel tavwl teleh tehdx data input
m48t35ay, M48T35AV 12/25 table 8. write mode ac characteristics note: 1. valid for ambient operating temperature: t a = 0 to 70c or C40 to 85c; v cc = 4.5 to 5.5v or 3.0 to 3.6v (except where noted). 2. c l = 5pf. 3. if e goes low simultaneously with w going low, the outputs remain in the high impedance state. symbol parameter (1) m48t35ay M48T35AV unit C70 C100 min max min max t avav write cycle time 70 100 ns t av wl address valid to write enable low 0 0 ns t av el address valid to chip enable low 0 0 ns t wlwh write enable pulse width 50 80 ns t eleh chip enable low to chip enable high 55 80 ns t whax write enable high to address transition 0 10 ns t ehax chip enable high to address transition 0 10 ns t dvwh input valid to write enable high 30 50 ns t dveh input valid to chip enable high 30 50 ns t whdx write enable high to input transition 5 5 ns t ehdx chip enable high to input transition 5 5 ns t wlqz (2,3) write enable low to output hi-z 25 50 ns t avw h address valid to write enable high 60 80 ns t ave h address valid to chip enable high 60 80 ns t whqx (2,3) write enable high to output transition 5 10 ns
13/25 m48t35ay, M48T35AV data retention mode with valid v cc applied, the m48t35ay/v operates as a conventional bytewide? static ram. should the supply voltage decay, the ram will au- tomatically power-fail deselect, write protecting it- self when v cc falls within the v pfd (max), vpfd (min) window (see figure 12, table 9, and table 10, page 14). all outputs become high impedance, and all inputs are treated as don't care. note: a power failure during a write cycle may corrupt data at the currently addressed location, but does not jeopardize the rest of the ram's con- tent. at voltages below v pfd (min), the user can be assured the memory will be in a write protected state, provided the v cc fall time is not less than t f . the m48t35ay/v may respond to transient noise spikes on v cc that reach into the deselect window during the time the device is sampling v cc . there- fore, decoupling of the power supply lines is rec- ommended. when v cc drops below v so , the control circuit switches power to the internal battery which pre- serves data and powers the clock. the internal button cell will maintain data in the m48t35ay/v for an accumulated period of at least 7 years when v cc is less than v so . as system power returns and v cc rises above v so , the battery is discon- nected and the power supply is switched to exter- nal v cc . write protection continues until v cc reaches v pfd (min) plus t rec (min). e should be kept high as v cc rises past v pfd (min) to prevent inadvertent write cycles prior to processor stabi- lization. normal ram operation can resume t rec after v cc exceeds v pfd (max). also, as v cc rises, the battery voltage is checked. if the voltage is less than approximately 2.5v, an internal battery not ok (bok ) flag will be set. the bok flag can be checked after power up. if the bok flag is set, the first write attempted will be blocked. the flag is automatically cleared after the first write, and normal ram operation resumes. figure 11 illustrates how a bok check routine could be structured. for more information on battery storage life refer to the application note an1012. figure 11. checking the bok flag status read data at any address ai00607 is data complement of first read? (battery ok) power-up yes no write data complement back to same address read data at same address again notify system of low battery (data may be corrupted) write original data back to same address (battery low) continue
m48t35ay, M48T35AV 14/25 figure 12. power down/up mode ac waveforms table 9. power down/up ac characteristics note: 1. valid for ambient operating temperature: t a = 0 to 70c or C40 to 85c; v cc = 4.5 to 5.5v or 3.0 to 3.6v (except where noted). 2. v pfd (max) to v pfd (min) fall time of less than t f may result in deselection/write protection not occurring until 200s after v cc pass- es v pfd (min). 3. v pfd (min) to v ss fall time of less than t fb may cause corruption of ram data. 4. t rec (min) = 20ms for industrial temperature grade 6 device. table 10. power down/up trip points dc characteristics note: 1. valid for ambient operating temperature: t a = 0 to 70c or C40 to 85c; v cc = 4.5 to 5.5v or 3.0 to 3.6v (except where noted). 2. all voltages referenced to v ss . 3. caphat and m4t32-br12sh1 snaphat only, m4t28-br12sh1 snaphat top t dr =7years(typ). 4. using larger m4t32-br12sh6 snaphat top (recommended for industrial temperature range - grade 6 device). 5. at 25c. symbol parameter (1) min max unit t pd e or w at v ih before power down 0s t f (2) v pfd (max) to v pfd (min) v cc fall time 300 s t fb (3) v pfd (min) to v ss v cc fall time m48t35ay 10 s M48T35AV 150 s t r v pfd (min) to v pfd (max) v cc rise time 10 s t rb v ss to v pfd (min) v cc rise time 1s t rec (4) v pfd (max) to inputs recognized 40 200 ms symbol parameter (1,2) min typ max unit v pfd power-fail deselect voltage m48t35ay 4.2 4.35 4.5 v M48T35AV 2.7 2.9 3.0 v v so battery back-up switchover voltage m48t35ay 3.0 v M48T35AV v pfd C100mv v t dr (5) expected data retention time grade 1 10 (3) years grade 6 10 (4) years ai01168c v cc inputs (per control input) outputs don't care high-z tf tfb tr tpd trb tdr valid valid (per control input) recognized recognized v pfd (max) v pfd (min) v so trec
15/25 m48t35ay, M48T35AV clock operations reading the clock updates to the timek eeper ? registers (see ta- ble 11) should be halted before clock data is read to prevent reading data in transition. the bi- port? timekeeper cells in the ram array are only data registers and not the actual clock counters, so updating the registers can be halted without disturbing the clock itself. updating is halted when a '1' is written to the read bit, d6 in the control register 7ff8h. as long as a '1' remains in that position, updating is halted. after a halt is issued, the registers reflect the count; that is, the day, date, and the time that were current at the moment the halt command was is- sued. all of the timekeeper registers are updated si- multaneously. a halt will not interrupt an update in progress. updating is within a second after the bit is reset to a '0.' setting the clock bit d7 of the control register 7ff8h is the write bit. setting the write bit to a '1,' like the read bit, halts updates to the timeke eper ? registers. the user can then load them with the correct day, date, and time data in 24 hour bcd format (see table 11, page 15). resetting the write bit to a '0' then transfers the values of all time registers 7ff9h-7fffh to the actual timekeeper counters and allows normal operation to resume. the ft bit and the bits marked as '0' in table 11 must be written to '0' to allow for normal time- keeper and ram operation. after the write bit is reset, the next clock update will occur within one second. see the application note an923, timek eeper ? rolling into the 21 st century for information on century rollover. stopping and starting the oscillator the oscillator may be stopped at any time. if the device is going to spend a significant amount of time on the shelf, the oscillator can be turned off to minimize current drain on the battery. the stop bit is the msb of the seconds register. setting it to a '1' stops the oscillator. the m48t35ay/v is shipped from stmicroelectronics with the stop bit set to a '1.' when reset to a '0,' the m48t35ay/ v oscillator starts within 1 second. table 11. register map keys: s = sign bit ft = frequency test bit (must be set to '0' upon power for normal operation) r = read bit w=writebit st = stop bit 0=mustbesetto'0' ceb = century enable bit cb = century bit note: when ceb is set to '1,' cb will toggle from '0' to '1' or from '1' to '0' at the turn of the century (dependent upon the initial value set). when ceb is set to '0,' cb will not toggle. the write bit does not need to be set to write to ceb. address data function/range bcd format d7 d6 d5 d4 d3 d2 d1 d0 7fffh 10 years year year 00-99 7ffeh 0 0 0 10 m. month month 01-12 7ffdh 0 0 10 date date date 01-31 7ffch 0 ft ceb cb 0 day century/day 00-01/01-07 7ffbh 0 0 10 hours hours hours 00-23 7ffah 0 10 minutes minutes minutes 00-59 7ff9h st 10 seconds seconds seconds 00-59 7ff8h w r s calibration control
m48t35ay, M48T35AV 16/25 calibrating the clock the m48t35ay/v is driven by a quartz-controlled oscillator with a nominal frequency of 32,768 hz. the devices are tested not to exceed 35 ppm (parts per million) oscillator frequency error at 25c, which equates to about 1.53 minutes per month. with the calibration bits properly set, the accuracy of each m48t35ay/v improves to better than +1/C2 ppm at 25c. the oscillation rate of any crystal changes with temperature (see figure 14, page 18). most clock chips compensate for crystal frequency and tem- perature shift error with cumbersome trim capac- itors. the m48t35ay/v design, however, employs periodic counter correction. the calibration circuit adds or subtracts counts from the oscillator divider circuit at the divide by 256 stage, as shown in fig- ure 15, page 18. the number of times pulses are blanked (subtracted, negative calibration) or split (added, positive calibration) depends upon the value loaded into the five calibration bits found in the control register. adding counts speeds the clock up, subtracting counts slows the clock down. the calibration byte occupies the five lower order bits (d4-d0) in the control register 7ff8h. these bits can be set to represent any value between 0 and 31 in binary form. bit d5 is the sign bit; '1' in- dicates positive calibration, '0' indicates negative calibration. calibration occurs within a 64 minute cycle. the first 62 minutes in the cycle may, once per minute, have one second either shortened by 128 or lengthened by 256 oscillator cycles. if a bi- nary '1' is loaded into the register, only the first 2 minutes in the 64 minute cycle will be modified; if a binary 6 is loaded, the first 12 will be affected, and so on. therefore, each calibration step has the effect of adding 512 or subtracting 256 oscillator cycles for every 125,829,120 actual oscillator cycles, that is +4.068 or C2.034 ppm of adjustment per calibra- tion step in the calibration register. assuming that the oscillator is in fact running at exactly 32,768 hz, each of the 31 increments in the calibration byte would represent +10.7 or C5.35 seconds per month which corresponds to a total range of +5.5 or C2.75 minutes per month. two methods are available for ascertaining how much calibration a given m48t35ay/v may re- quire. the first involves simply setting the clock, letting it run for a month and comparing it to a known accurate reference (like wwv broadcasts). while that may seem crude, it allows the designer to give the end user the ability to calibrate his clock as his environment may require, even after the fi- nal product is packaged in a non-user serviceable enclosure. the second approach is better suited to a manu- facturing environment, and involves the use of some test equipment. when the frequency test (ft) bit, the seventh-most significant bit in the day register is set to a '1,' and d7 of the seconds reg- ister is a '0' (oscillator running), dq0 will toggle at 512 hz during a read of the seconds register. any deviation from 512 hz indicates the degree and direction of oscillator frequency shift at the test temperature. for example, a reading of 512.01024 hz would indicate a +20 ppm oscillator frequency error, requiring a C10 (wr001010) to be loaded into the calibration byte for correction. note: setting or changing the calibration byte does not affect the frequency test output fre- quency. the ft bit must be reset to '0' for normal clock operations to resume. the ft bit is automatically reset on power-down. for more information on calibration, see applica- tion note an934, timeke eper ? calibration. century bit bit d5 and d4 of clock register 7ffch contain the century enable bit (ceb) and the cen- turybit(cb).settingcebtoa'1'willcausecb to toggle, either from a '0' to '1' or from '1' to '0' at the turn of the century (depending upon its initial state). if ceb is set to a '0,' cb will not toggle. note: the write bit must be set in order to write to the century bit.
17/25 m48t35ay, M48T35AV v cc noise and negative going transients i cc transients, including those produced by output switching, can produce voltage fluctuations, re- sultinginspikesonthev cc bus. these transients can be reduced if capacitors are used to store en- ergy which stabilizes the v cc bus. the energy stored in the bypass capacitors will be released as low going spikes are generated or energy will be absorbed when overshoots occur. a bypass ca- pacitor value of 0.1f (as shown in figure 13) is recommended in order to provide the needed fil- tering. in addition to transients that are caused by normal sram operation, power cycling can generate neg- ative voltage spikes on v cc that drive it to values below v ss by as much as one volt. these negative spikes can cause data corruption in the sram while in battery backup mode. to protect from these voltage spikes, it is recommended to con- nect a schottky diode from v cc to v ss (cathode connected to v cc , anode to v ss ). schottky diode 1n5817 is recommended for through hole and mbrs120t3 is recommended for surface mount. figure 13. supply voltage protection ai02169 v cc 0.1 m f device v cc v ss
m48t35ay, M48T35AV 18/25 figure 14. crystal accuracy across temperature figure 15. clock calibration ai02124 -80 -60 -100 -40 -20 0 20 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 d f = -0.038 (t - t 0 ) 2 10% f ppm c 2 t 0 = 25 c ppm c ai00594b normal positive calibration negative calibration
19/25 m48t35ay, M48T35AV part numbering table 12. ordering information scheme note: 1. the soic package (soh28) requires the battery package (snaphat ? ) which is ordered separately under the part number m4txx-br12sh in plastic tube or m4txx-br12shtr in tape & reel form. 2. available in soic package only. caution : do not place the snaphat battery package m4txx-br00sh in conductive foam as it will drain the lithium button-cell battery. for a list of available options (e.g., speed, package) or for further information on any aspect of this device, please contact the st sales office nearest to you. table 13. snaphat battery table example: m48t 35ay C70 mh 1 tr device type m48t supply voltage and write protect voltage 35ay = v cc = 4.5 to 5.5v; v pfd = 4.2 to 4.5v 35av = v cc = 3.0 to 3.6v; v pfd = 2.7 to 3.0v speed C70 = 70ns (35ay) C10 = 100ns (35av) package pc = pcdip28 mh (1) = soh28 temperature range 1 = 0 to 70c 6 = C40 to 85c (2) shipping method for soic blank = tubes tr = tape & reel part number description package m4t28-br12sh lithium battery (48mah) snaphat sh m4t32-br12sh lithium battery (120mah) snaphat sh
m48t35ay, M48T35AV 20/25 package mechanical information figure 16. pcdip28 C 28-pin plastic dip, battery caphat, package outline note: drawing is not to scale. table 14. pcdip28 C 28-pin plastic dip, battery caphat, package mechanical data symb mm inches typ min max typ min max a 8.89 9.65 0.350 0.380 a1 0.38 0.76 0.015 0.030 a2 8.38 8.89 0.330 0.350 b 0.38 0.53 0.015 0.021 b1 1.14 1.78 0.045 0.070 c 0.20 0.31 0.008 0.012 d 39.37 39.88 1.550 1.570 e 17.83 18.34 0.702 0.722 e1 2.29 2.79 0.090 0.110 e3 29.72 36.32 1.170 1.430 ea 15.24 16.00 0.600 0.630 l 3.05 3.81 0.120 0.150 n28 28 pcdip a2 a1 a l b1 b e1 d e n 1 c ea e3
21/25 m48t35ay, M48T35AV figure 17. soh28 C 28-lead plastic small outline, 4-socket battery snaphat, package outline note: drawing is not to scale. table 15. soh28 C 28-lead plastic small outline, 4-socket battery snaphat, package mechanical data symb mm inches typ min max typ min max a 3.05 0.120 a1 0.05 0.36 0.002 0.014 a2 2.34 2.69 0.092 0.106 b 0.36 0.51 0.014 0.020 c 0.15 0.32 0.006 0.012 d 17.71 18.49 0.697 0.728 e 8.23 8.89 0.324 0.350 e 1.27 C C 0.050 C C eb 3.20 3.61 0.126 0.142 h 11.51 12.70 0.453 0.500 l 0.41 1.27 0.016 0.050 a 0 8 0 8 n28 28 cp 0.10 0.004 soh-a e n d c l a1 a 1 h a cp be a2 eb
m48t35ay, M48T35AV 22/25 figure 18. sh C 4-pin snaphat housing for 48mah battery & crystal, package outline note: drawing is not to scale. table 16. sh C 4-pin snaphat housing for 48mah battery & crystal, package mechanical data symb mm inches typ min max typ min max a 9.78 0.385 a1 6.73 7.24 0.265 0.285 a2 6.48 6.99 0.255 0.275 a3 0.38 0.015 b 0.46 0.56 0.018 0.022 d 21.21 21.84 0.835 0.860 e 14.22 14.99 0.560 0.590 ea 15.55 15.95 0.612 0.628 eb 3.20 3.61 0.126 0.142 l 2.03 2.29 0.080 0.090 shtk-a a1 a d e ea eb a2 b l a3
23/25 m48t35ay, M48T35AV figure 19. sh C 4-pin snaphat housing for 120mah battery & crystal, package outline note: drawing is not to scale. table 17. sh C 4-pin snaphat housing for 120mah battery & crystal, package mechanical data symb mm inches typ min max typ min max a 10.54 0.415 a1 8.00 8.51 0.315 0.335 a2 7.24 8.00 0.285 0.315 a3 0.38 0.015 b 0.46 0.56 0.018 0.022 d 21.21 21.84 0.835 0.860 e 17.27 18.03 0.680 0.710 ea 15.55 15.95 0.612 0.628 eb 3.20 3.61 0.126 0.142 l 2.03 2.29 0.080 0.090 shtk-a a1 a d e ea eb a2 b l a3
m48t35ay, M48T35AV 24/25 revision history table 18. document revision history date revision details november 1999 first issue 04/21/00 from preliminary data to data sheet 05/29/00 t fb change (table 9) 07/20/01 reformatted; temp./voltage info. added to tables (table 4, 5, 7, 8, 9, 10); add century bit text 05/20/02 modify reflow time and temperature footnotes (table 2)
25/25 m48t35ay, M48T35AV information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectronics. the st logo is registered trademark of stmicroelectronics all other names are the property of their respective owners. ? 2002 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - brazil - canada - china - finland - france - germany - hong kong - india - israel - italy - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - u.s.a. www.st.com

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